1. Field of the Invention
The present invention relates generally to a fabrication process of a compound semiconductor device. More specifically, the invention relates to a fabrication process of a compound semiconductor device, which includes an improved process for formation of a gate electrode.
2. Description of the Related Art
In a compound semiconductor device frequently used as an amplifier element at a microwave band and an extreme high frequency band, a gate electrode having T-shaped cross-section is employed for shortening gate length (hereinafter referred to as "Lg") and providing large cross-sectional area of the gate electrode, for improving a high frequency characteristics.
FIG. 1A is a section showing one example of the conventional compound semiconductor device having T-shaped gate electrode. As shown in FIG. 1A, a source electrode 9 and a drain electrode 10 are formed on a GaAs substrate 1. On the surface of the substrate at the position between the source electrode 9 and the drain electrode, a gate electrode 8 having T-shaped cross-section is formed.
However, in the conventional compound semiconductor device having the T-shaped gate electrode 8, due to presence of "overhanging portion" of the gate electrode 8, a parasitic capacitance between the gate electrode and the source and drain electrodes 9 and 10 is increased. Among these parasitic capacitances, the parasitic capacitance C.sub.GS2 between the gate and source is smaller than an intrinsic capacitance C.sub.GS1 and thus gives little influence to the characteristics of the device. On the other hand, the parasitic capacitance C.sub.GD2 between the gate electrode and the drain electrode significantly influences to the characteristics of the device since the intrinsic capacitance C.sub.GD1 between the gate electrode and the drain electrode is small. Therefore, increasing of the parasitic capacitance inherently causes lowering of a maximum effective power gain which degrades high frequency characteristics of the device.
One example of a solution for this has been disclosed in Japanese Unexamined Utility Model Publication (Kokai) No. Showa 63-188964, in which is disclosed a compound semiconductor device having a substantially reversed L-shaped gate electrode having the "overhanging portion" at the side of the source, as shown in FIG. 1B. Namely, while the compound semiconductor device illustrated in FIG. 1B has the overhanging portion extending toward the source electrode 9, the gate electrode does not extend toward the drain electrode 10. With this construction, high frequency characteristics can be improved without increasing the gate-drain parasitic capacity.
FIGS. 2A to 2E are sections showing steps in fabrication of the conventional compound semiconductor device shown in FIG. 1B.
At first, on the GaAs substrate 1 formed with an active layer, a silicon oxide film of 400 nm thick is formed by way of LPCVD method. Then, employing an etching gas, such as CHF.sub.3, CF.sub.4 or SF.sub.4 and so forth, the silicon oxide film is selectively dry-etched to form an opening 2a for forming the gate electrode by lithographic technology.
Then, on the surface, side surface of the silicon oxide layer including the opening and the surface of the substrate 1 within the opening 2a, a 200 nm thick tungsten silicide (WSi) layer, a 100 nm thick titanium nitride (TIN) layer and a 20 nm thick platinum (Pt) layer are stacked in order by deposition method or sputtering method. A stacked layer 6 (hereinafter also referred to as WSi.cndot.TiN.cndot.Pt film) thus formed forms a part of the gate electrode.
Next, as shown in FIG. 2B, a photoresist layer 4 with a reversed taper form opening is formed on the surface including the opening portion 2a by way of image reversing method or lithographic technology. At this time, the side surface 4a of the opening portion of the photoresist layer 4 at the side of the drain electrode is aligned with the side wall of the gate electrode forming opening portion 2a. On the other hand, the side surface 4b of the opening portion of the photoresist layer 4 at the side of the source electrode is shifted away from the edge of the gate electrode forming opening portion 2a to the extent of 0.2 to 1.0 .mu.m.
Next, as shown in FIG. 2C, using the photoresist layer 4 as a mask, a 700 nm thick gold (Au) layer is plated on the WSi.cndot.TiN.cndot.Pt layer 6 to form the reversed L-shaped gate electrode 8.
Subsequently, as shown in FIG. 2D, after removing the photoresist layer 4, using the gate electrode 8 as a mask, etching of the WSi.cndot.TiN.cndot.Pt layer 6 is performed with a reactive ion etching method (hereinafter referred to as RIE) to remove the portion not covered by the gate electrode 8. At this time, by removing the WSi.cndot.TiN.cndot.Pt layer 6 employing BCl.sub.3 type gas or Cl.sub.2 /CF.sub.4 type gas, the etching amount of the gate electrode formed of the Au layer can be limited to be approximately 100 nm.
Next, as shown in FIG. 2E, the silicon oxide layer 2 at the positions of the source electrode and the drain electrode is selectively removed, and the source electrode 9 and the drain electrode 10 are formed selectively.
Through the process set forth above, the semiconductor device having the reversed L-shaped gate electrode having the overhanging portion only at the side of the source electrode is thus formed.
However, since the above-mentioned conventional compound semiconductor device fabrication method forms the reversed L-shaped gate electrode by aligning the side surface 4a of the opening portion of the photoresist layer for masking in plating at the side of the drain electrode to the side wall of the gate electrode forming the opening portion 2a, and shifting the side surface 4b at the side of the source electrode away from the edge of the gate electrode forming opening portion 2a to the extent of 0.2 to 1.0 .rho.m, the margin when the mask for the photoresist layer 4 is aligned is zero.
FIGS. 3A and 3B and FIGS. 4A and 4B are sections of a semiconductor chip during the fabrication process for illustrating problems in the conventional compound semiconductor device fabrication process.
At first, as shown in FIG. 3A, when the side surface 4a of the opening portion of the photoresist layer at the side of the drain electrode is offset from the edge of the gate electrode forming opening portion 2a toward the drain electrode in the magnitude of Da, the gate electrode 8 becomes T-shaped configuration instead of the reversed L-shaped configuration, as shown in FIG. 3B. In this case, the gate-drain parasitic capacity C.sub.GD2 becomes large to lower the maximum effective power gain and thus causes degradation of the high frequency characteristics.
On the other hand, as shown in FIG. 4A, when the side surface 4a of the opening portion of the photoresist layer 4 at the side of the drain electrode is offset from the edge of the gate electrode forming opening portion 2a toward the source electrode in the magnitude of Db, while the reversed L-shaped gate electrode is formed, the gate length thereof becomes shorter than the desired value as shown in FIG. 4B to make it impossible to attain the desired high frequency characteristics. Furthermore, residue of the WSi.cndot.TiN.cndot.Pt layer as the first metal layer within the gate electrode forming opening portion 2a can be caused. Such residual WSi.cndot.TiN.cndot.Pt layer may cause leakage between the electrodes to degrade characteristics of the device.